The present application relates to a latch, for example, such as used in a domino-logic address decoding circuit.
Domino logic is a type of sequential circuitry used, for example, in CMOS (Complementary Metal Oxide Silicon) logic applications such as VLSI (Very Large Scale Integration) semiconductor design. Typically, a domino logic circuit is formed of a cascaded set of dynamic logic elements in which each stage evaluates and causes the next stage to evaluate, similar to the manner in which each domino in a row topples its neighbor. As a result, a single clock can be used to precharge and evaluate a cascaded set of dynamic logic circuits.
As shown in FIG. 1, a conventional CMOS domino-logic circuit 100 may be formed of two different blocks: a dynamic CMOS block 102 and a domino logic block 104. The dynamic CMOS block 102, in turn, is formed of a precharge transistor 103 (e.g., a p-type transistor) that is configured to precharge a sensing node 101 during the precharge clock phase (e.g., CLK=0) to a predetermined logic level (e.g., VDD or high), a logic block 105 (e.g., formed of n-type devices) that receives and evaluates inputs, and a discharge transistor 107 (e.g., an n-type transistor) that, during the evaluate clock phase (e.g., CLK=1) and depending on the make-up of logic block 105 and the inputs that it receives, conditionally discharges the sensing node 101 to another logic level (e.g., VSS or low). The domino block 104 typically is formed of a transistor 109 (e.g., a p-type device) and a static inverter 111.
As an alternative to the transistor types shown in FIG. 1, a n-type transistor that precharges the sensing node to VSS could be used as precharge transistor 103, a p-type transistor that conditionally discharges the sensing node 101 to VDD could be used as discharge transistor 107, and an n-type transistor could be used in place of domino block transistor 109, in which case the logic block 105 may be formed of p-type devices.
Domino logic frequently is used in decoders. Decoders often are used to select an appropriate portion of a computer memory (e.g., at which a read or write operation is to be performed) depending upon the particular address input to the decoder.